kw.\*:("Delayed clocks")
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A technique- for improving dual-output domino logicRAMPRASAD, Sumant; HAJJ, Ibrahim N; NAJM, Farid N et al.IEEE transactions on very large scale integration (VLSI) systems. 2002, Vol 10, Num 4, pp 508-511, issn 1063-8210, 4 p.Article
Chip-package hybrid clock distribution network and DLL for low jitter clock deliveryCHUNG, Daehyun; RYU, Chunghyun; KIM, Hyungsoo et al.IEEE journal of solid-state circuits. 2006, Vol 41, Num 1, pp 274-286, issn 0018-9200, 13 p.Conference Paper